Electrically-erasable, programmable read-only memories (EEPROMs) employing single transistor memory cells (also referred to as bits), and which use hot carrier injection for programming and Fowler-Nordheim tunneling for erasure are in wide usage, and have been described, for example, in "A Single Transistor EEPROM Bit and its Implementation in a 512K CMOS EEPROM(s)," Mukheree, et al., IEDM 1985, pp. 616-619, and "A 90 NS 100K Erase/Program Cycle Megabit Flash Memory," V. Kynett, et al., ISSCC 1989, pp. 140-141.
Such EEPROMs are programmed via hot-electron injection to a floating gate by the application of high voltage to the control gate and drain of a particular memory bit while keeping the source of that memory bit grounded. For example, the drain programming voltage, V.sub.dp is kept below 6.5 volts while the control gate programming voltage, V.sub.cgp is held at 12 volts. Erasing is accomplished by maintaining the control gate voltage at V.sub.cge =0 volts, floating the drain, and raising the source to V.sub.se =12 volts. Erased cells conduct, and programmed cells do not conduct, with their control gates raised to a read voltage of approximately 5 volts. The above-described examples are for explanation only, it being understood that other voltages may be used to accomplish the same effect.
A particular type of EEPROM, known as a flash EEPROM, divides memory bits into various sectors. Within each sector, the source of each memory bit transistor is tied to a common node. Thus, erasure can be performed only on a sector-by-sector basis, or on different sectors in parallel. The control gates of the memory bit transistors are coupled to wordlines, and their drains to bitlines.
When sectors are physically separated on an integrated circuit, erasure of a particular sector has little effect on other sectors. However, physical separation of sectors requires an area penalty, and thus in applications where memory density is important, physical separation is unattractive.
Without physical separation, memory cells within different sectors may share the same bitlines, and thus, voltages placed on these bitlines produce electrical field effects on all sectors sharing these bitlines. Furthermore, memory cells within different sectors may share wordlines, and voltages on these shared wordlines create field effects in all sectors sharing them.
The electric fields generated on the shared bitlines and wordlines may have the effect of erasing programmed bits or programming erased bits. For example, raising the voltage on a wordline to program an erased bit may disturb a previously programmed bit on the same wordline by removing some electrons from the floating gate to the control gate of the previously programmed bit. This type of disturbance is known as wordline stress.
Another type of wordline stress, known as wordline stress up or wordline softwrite, occurs when an otherwise erased bit has its wordline raised to a high voltage due to programming of another bit on the same wordline. This disturb condition results in the addition of electrons to the floating gate of the erased bit by tunneling of electrons from the channel.
With shared bitlines, a disturbance known as bitline stress often occurs. Bitline stress occurs when a previously programmed bit has its drain raised to a high voltage as a result of programming another bit on the same bitline. This disturbed condition results in the removal of electrons from the floating gate of the previously programmed bit through diffusion.
EEPROMS can typically withstand a large number, such as 10,000, erase cycles before their performance deteriorates to the point that they cannot meet their rated specifications. Consequently, the amount of time that a particular bit in a sectored chip experiences a disturb condition, such as bitline or wordline stress, may become very large in flash EEPROMS. For example, a programmed bit in a given sector may experience 10,000periods of bitline stress if it remains in a single program state while bits in other sectors which share the same bitline are repeatedly programmed and erased. The longer that bits experience disturb conditions, the more likely it is that they will lose data, either by converting from an erased state to a programmed state, or from a programmed state to an erased state. Such data loss or gain is unacceptable.
Therefore, a need has arisen for a method and apparatus for refreshing EEPROM bits to prevent data loss.